• VortexLink
  • $113,140.00 -164,440.00/year*
  • Campbell, CA
  • Engineering
  • Full-Time
  • 350 Budd Ave

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You will work with ASIC Front-end RTL teams, backend physical design teams to understand chip architecture and drive design for test requirements early in the design cycle. As a member of this team you will be involved in creating cutting edge next generation hellip.. chips. You will be the lead to drive the DFT and quality process through the entire Implementation flow. ASIC Design for Test Hardware Engineer with 8+ years of related work experience with a broad mix of technologies including Excellent knowledge of latest state-of-the-art trends in DFT and test. Hands-on experience with Jtag protocols, Scan and BIST architectures, including Logic BIST, memory BIST, IO BIST Verification skills include, System Verilog, UVM, Logic Equivalency checking and validating the Test-timing of the design. Experience working with Gate level simulation, and debug with VCS and other simulators. Post-silicon validation and debug experience Ability to work with ATE patterns, P1687 Strong verbal communication skills and ability to thrive in a dynamic environment Scripting skills PythonPerl. Bachelor's or a Masterrsquos Degree in Electrical or Computer Engineering required
Associated topics: asic, c++, circuit, rtos, smt, submicron, surface mount, transistor, verilog, vhdl

* The salary listed in the header is an estimate based on salary data for similar jobs in the same area. Salary or compensation data found in the job description is accurate.

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